Method of forming landing pads for bit line and node contact
US6117757A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Oct 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming landing pads for a bit line and a node contact is provided. First, a first dielectric layer is formed on a substrate having a transistor structure thereon. The first dielectric layer is defined and etched in a self-aligned process to form a contact opening to the substrate. A second dielectric layer is formed on the first dielectric layer and is etched back to form a spacer on the opening sidewall. Then, a conductive layer is formed on the first dielectric layer and fills the opening. A bit line is formed by partially removing the conductive layer through a photo-resist mask provided on the conductive layer, wherein the conductive layer filling the opening is left to form a landing pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.