Method of forming an integrated circuit structure
US6117767A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 5, 1999 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Feb 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Silicon-rich silicon nitride is employed as a protective layer in a self-aligning etch. A thin layer of silicon-rich silicon nitride is deposited conformably over raised structures on a substrate. An etchable layer is then deposited, filling a space between the raised structures and providing a horizontal top surface. A mask layer is then formed on the etchable layer and patterned to expose an area of the etchable layer over the space between the raised structures. The etchable layer is then etched with an etchant selective to silicon nitride to remove the etchable layer from between the raised structures. Then the space between the raised structures is filled with a fill material, forming a self-aligned structure comprised of said fill material and self-aligned to the raised structures. The thin layer of silicon-rich silicon nitride resists the etch of the etchable layer better than the typical stoichiometric silicon nitride, providing increased selectivity, improving the reliability of the self-aligning process by preventing etch-through of protective layers, and thereby improving process control and yield of the self-aligning process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.