Stacked chip assembly utilizing a lead frame
US6118176A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1999 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Apr 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked chip assembly generally includes a first chip, a second chip and a lead frame. The lower surface of the first chip is pasted onto the lower surface of the second chip by an adhesive film so as to form a stacked chip body. The stacked chip body is disposed on the lead frame. Bonding pads of the upper surface of the first chip are interconnected to the upper surface of the inner leads of the lead frame by bonding wires. Bonding pads of the upper surface of the second chip are interconnected to the lower surface of the inner leads of the lead frame by bonding wires. Therefore, the first chip and the second chip are simultaneously interconnected to an external circuit devices through the lead frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.