Process architecture and manufacturing tool sets employing hard mask patterning for use in the manufacture of one or more metallization levels on a workpiece
US6120641A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1998 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Aug 3, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing tool configuration for applying one or more levels of interconnect metallization to a generally planar dielectric surface of a workpiece with a minimal number of workpiece transfer operations between the tool sets is disclosed. The tool configuration comprises a film deposition tool set, a hard mask formation tool set, a hard mask etching tool set, a pattern processing tool set, a wet processing tool set, and a dielectric processing tool set. The film deposition tool set is used to deposit a conductive barrier layer exterior to the planar dielectric surface of the workpiece and a conductive seed layer exterior to the barrier layer. The hard mask formation tool set is used to form a hard mask dielectric layer exterior to the seed layer in accordance with one of the disclosed processes, and to form a still further hard mask dielectric layer exterior to the hard mask dielectric layer. In accordance with a first disclosed process, the pattern processing tool set is used to provide an interconnect line pattern over the hard mask dielectric layer and to provide a post pattern over interconnect line metallization formed using the interconnect line pattern. In accordance wi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.