Method of fabricating a MOS transistor with a raised source/drain extension
US6121100A · kind A · utility
86Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1997 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Dec 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a MOS transistor. According to the method of the present invention, a pair of source/drain contact regions are formed on opposite sides of a gate electrode. After forming the pair of source/drain contact regions, semiconductor material is deposited onto opposite sides of the gate electrode. Dopants are then diffused from the semiconductor material into the substrate beneath the gate electrode to form a pair of source/drain extensions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.