Method of forming hemispherical grain polysilicon over lower electrode capacitor

US6121109A · kind A · utility

Assignee

• United Semiconductor Corp. · TW

Inventors

• Shih-Ching Chen · Taipei, TW
• Neng-Hsing Shen · Hengshan, TW

Key dates

• Filing date: Nov 13, 1998
• Grant date: Sep 19, 2000
• Expiry date: Nov 13, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/033

Abstract

A method of forming a layer of hemispherical grain polysilicon over the lower electrode of a capacitor. The method comprises the steps of providing a substrate that has a field effect transistor already formed thereon, and then forming an insulating layer with a contact opening over the substrate. Subsequently, a polysilicon layer is formed over the insulating layer that completely fills the contact opening. This polysilicon layer is electrically coupled to one of the source/drain regions of the field effect transistor. Thereafter, a thin buffer layer is formed over the polysilicon layer, and then the thin buffer layer is patterned. The thin buffer layer is used as a mask for covering the polysilicon layer that is to be part of the lower electrode of a capacitor. Next, a plasma etching operation is carried out to remove the thin buffer layer and a portion of the polysilicon layer at the same time. Finally, a heat treatment is carried out to form a hemispherical grain polysilicon layer over the surface of the lower electrode.