Sputter-resistant hardmask for damascene trench/via formation
US6121150A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1999 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Apr 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The dimensional precision and accuracy of sub-micron-sized, in-laid metallization patterns, e.g., of electroplated copper or copper alloy, formed in the surface of a dielectric layer are significantly improved by utilizing a layer of a sputter-resistant mask material formed of a high atomic mass metallic element or compound thereof during reactive ion etching of the dielectric layer by a fluorine-containing plasma for forming sub-micron-dimensioned recesses therein. After filling of the recesses, planarization, as by CMP, is conducted wherein excess thickness of the metal layer is removed, together with underlying portions of the sputter-resistant mask layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.