Inventor · San Jose, CA, US

Fei Wang

240Patents
30h-index
304Co-inventors
93Inventor score

Filing activity: May 1, 1990 → Aug 9, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US6528409B1 Interconnect structure formed in porous dielectric material with minimized degradation and electromigration Electricity 394 Expired
US6537881B1 Process for fabricating a non-volatile memory device Electricity 194 Expired
US9721789B1 Saving ion-damaged spacers Electricity 114 Active
US6117781A Optimized trench/via profile for damascene processing Electricity 90 Expired
US6184128A Method using a thin resist mask for dual damascene stop layer etch Electricity 74 Expired
US6057239A Dual damascene process using sacrificial spin-on materials Electricity 72 Expired
US6020269A Ultra-thin resist and nitride/oxide hard mask for metal etch Electricity 65 Expired
US7880958B2 Display cell structure and electrode protecting layer compositions Physics 55 Active
US6117782A Optimized trench/via profile for damascene filling Electricity 52 Expired
US6060380A Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication Electricity 49 Expired
US6271087A Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects Electricity 44 Expired
US6440640B1 Thin resist with transition metal hard mask for via etch application Electricity 43 Expired
US5907781A Process for fabricating an integrated circuit with a self-aligned contact Electricity 41 Expired
US6165695A Thin resist with amorphous silicon hard mask for via etch application Emerging Cross-Sectional Technologies 41 Expired
US6040619A Semiconductor device including antireflective etch stop layer Electricity 40 Expired
US6562683B1 Bit-line oxidation by removing ONO oxide prior to bit-line implant Electricity 39 Expired
US6309926A Thin resist with nitride hard mask for gate etch application Electricity 39 Expired
US6312874A Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials Electricity 38 Expired
US6121150A Sputter-resistant hardmask for damascene trench/via formation Electricity 36 Expired
US6309955A Method for using a CVD organic barc as a hard mask during via etch Electricity 35 Expired
US6235628A Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer Electricity 35 Expired
US5920796A In-situ etch of BARC layer during formation of local interconnects Electricity 35 Expired
US6475929B1 Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant Electricity 34 Expired
US6528390B2 Process for fabricating a non-volatile memory device Electricity 33 Expired
US9576815B2 Gas-phase silicon nitride selective etch Electricity 33 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.