Semiconductor flip-chip package and method for the fabrication thereof
US6121689A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1998 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Jul 21, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/321
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A simplified process for flip-chip attachment of a chip to a substrate is provided by pre-coating the chip with an encapsulant underfill material having separate discrete solder columns therein to eliminate the conventional capillary flow underfill process. Such a structure permits incorporation of remeltable layers for rework, test, or repair. It also allows incorporation of electrical redistribution layers. In one aspect, the chip and pre-coated encapsulant are placed at an angle to the substrate and brought into contact with the pre-coated substrate, then the chip and pre-coated encapsulant are pivoted about the first point of contact, expelling any gas therebetween until the solder bumps on the chip are fully in contact with the substrate. There is also provided a flip-chip configuration having a complaint solder/flexible encapsulant understructure that deforms generally laterally with the substrate as the substrate undergoes expansion or contraction. With this configuration, the complaint solder/flexible encapsulant understructure absorbs the strain caused by the difference in the thermal coefficients of expansion between the chip and the substrate without bending the chip and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.