Bit by bit APDE verify for flash memory applications
US6122198A · kind A · utility
45Cited by
4References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 5, 1999 |
| Grant date | Sep 19, 2000 |
| Priority date | — |
| Expiry date | Oct 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of erase verifying and overerase verifying an array of flash memory cells by erase verifying each memory cell bit-by-bit in a memory array, overerase verifying each memory cell bit-by-bit in the memory array after each memory cell verifies as erased and again erase verifying each memory cell bit-by-bit in the memory array after each cell overerase verifies. The threshold voltage of each memory cell is compared to the threshold voltage of a reference memory cell and an overerase correction pulse is applied to the column in which the overerased memory cell is located.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.