Patent · US Expired

Method of margin testing programmable interconnect cell

US6122209A · kind A · utility

13Cited by

35References

15Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Christopher J. Pass · San Jose, US
James D. Sansbury · Portola Valley, US
Raminda Udaya Madurawe · Sunnyvale, US
John E. Turner · Beaverton, US
Rakesh Patel · Cupertino, US
Peter J. Wright · Stavanger, NO

Key dates

Filing date	Jul 8, 1999
Grant date	Sep 19, 2000
Priority date	—
Expiry date	Jul 8, 2019

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/1778
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.