Process for manufacturing a CMOS circuit with all-around dielectrically insulated source-drain regions

US6124156A · kind A · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Dietrich Widmann · Unterhaching, DE
• Martin Kerber · Munich, DE

Key dates

• Filing date: Feb 20, 1998
• Grant date: Sep 26, 2000
• Expiry date: Feb 20, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/601
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A CMOS circuit has all-around dielectrically insulated source-drain regions. Trenches are formed in the source-drain regions. The trenches are etched into the mono-crystalline silicon and filled with undoped or very lightly doped silicon. The completely or nearly completely depleted silicon in the trenches represents a dielectrically insulating layer and insulates the source-drain regions towards the adjacent silicon substrate.