Method for simultaneously forming a storage-capacitor electrode and interconnect
US6124199A · kind A · utility
22Cited by
29References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1999 |
| Grant date | Sep 26, 2000 |
| Priority date | — |
| Expiry date | Apr 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.