Patent · US Expired

Circuit configuration and method for automatic recognition and elimination of word line/bit line short circuits

US6125066A · kind A · utility

3Cited by

3References

5Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thoralf Gratz · Dresden, DE
Patrick Heyne · Hersbruck, DE
Dieter Harle · Hersbruck, DE

Key dates

Filing date	Mar 26, 1999
Grant date	Sep 26, 2000
Priority date	—
Expiry date	Mar 26, 2019

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/02
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit configuration and a method for automatic recognition and elimination of word line/bit line short circuits in a memory cell configuration containing sensor amplifiers, in which the sensor amplifiers split the memory cell configuration into memory blocks. To this end, a fuse is provided in the bit lines in each memory block upstream of the respective sensor amplifiers, the fuse being blown as a result of an appropriate voltage difference being applied in a test mode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.