Semiconductor device
US6130114A · kind A · utility
Assignee
Inventors
- Gen Murakami
- Kunihiro Tsubosaki
- Masahiro Ichitani
- Kunihiko Nishi
- Ichiro Anjoh
- Asao Nishimura
- Makoto Kitano
- Akihiro Yaguchi
- Sueo Kawai
- Masatsugu Ogata
- Syuuji Eguchi
- Hiroyoshi Kokaku
- Masanori Segawa
- Hiroshi Hozoji
- Takashi Yokoyama
- Noriyuki Kinjo
- Aizo Kaneda
- Junichi Saeki
- Shozo Nakamura
- Akio Hasebe
- Hiroshi Kikuchi
- Isamu Yoshida
- Takashi Yamazaki
- Kazuyoshi Oshima
- Tetsurou Matsumoto
Key dates
| Filing date | Apr 13, 1999 |
| Grant date | Oct 10, 2000 |
| Priority date | — |
| Expiry date | Apr 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3421
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.