Method of encapsulating a microelectronic assembly utilizing a barrier
US6130116A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1997 |
| Grant date | Oct 10, 2000 |
| Priority date | — |
| Expiry date | Dec 4, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/92122
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of encapsulating a microelectronic assembly includes providing one or more microelectronic assemblies having one or more elements defining exterior surfaces and an array of terminals exposed at the exterior surfaces, the one or more elements defining one or more apertures through the exterior surfaces. A layer of a curable barrier material is then provided on a supporting element. The barrier layer has openings therein in a pattern corresponding to the array of terminals on the one or more microelectronic assemblies. The supporting element and the one or more microelectronic elements are then assembled together so that the layer of barrier material contacts the exterior surfaces and covers the apertures and so that the openings in the layer of barrier material are aligned with the terminals. The barrier material is then cured while in contact with the exterior surfaces to thereby form a barrier layer covering the apertures. Next, a curable liquid encapsulant is applied to the microelectronic assemblies, whereby the barrier layer prevents the curable liquid encapsulant from flowing through the apertures, and the encapsulant is cured. The barrier layer and the supporting ele…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.