Address decoding scheme for DDR memory
US6130853A · kind A · utility
25Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1998 |
| Grant date | Oct 10, 2000 |
| Priority date | — |
| Expiry date | Mar 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits and a method are disclosed for a semiconductor memory which decode from a system supplied input address two outputs which are either adjacent or boundary adjacent to each other. The two decoded outputs derived from the input address select then, in one cycle, two locations in a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). The circuits producing the two decoded outputs allow for sequential and interleaved mode, for data bursts of various lengths, and for addressing of redundant columns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.