Method for creating diffusion areas for sources and drains without an etch step
US6133095A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Feb 4, 1999 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Feb 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
Abstract
A method for manufacturing a memory array having a plurality of memory cells thereon and diffusion areas therebetween includes the steps of laying down a layer of silicon nitride, defining the diffusion areas and creating diffusion oxides over the diffusion areas. Both steps of laying down and defining occur without etching any part of the layer of silicon nitride. The step of creating diffusion oxides includes the steps of creating porous silicon nitride from portions of the silicon nitride layer wherever diffusion oxides are desired (typically by laying down photoresist in a desired pattern and bombarding the silicon nitride layer with ions) and oxidizing both the porous silicon nitride and the silicon substrate through the porous silicon nitride thereby to create silicon oxy-nitride and silicon dioxide, respectively. The present invention also includes a semiconductor chip having diffusion or bit line oxides formed of at least silicon oxy-nitride.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.