Methods of forming trench isolation regions having conductive shields therein
US6133116A · kind A · utility
40Cited by
11References
6Claims
0Family size
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Key dates
| Filing date | Jun 9, 1999 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Jun 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Narrow-channel effect free DRAM cell transistor structure for submicron isolation pitch DRAMs having lowed-doped substrate and active width-independent threshold voltage by employing conductive shield in the shallow trench isolation(STI). The resulting cell transistor structure is highly immune to parasitic E-field penetration from the gate and neighbouring storage node junctions via STI and will be very appropriate for Gbit scale DRAM technology. The conductive shield is biased with the negative voltage in order to minimize the sidewall depletion in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.