High speed IC package configuration
US6133622A · kind A · utility
105Cited by
10References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1997 |
| Grant date | Oct 17, 2000 |
| Priority date | — |
| Expiry date | Dec 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Devices and methods for reducing lead inductance in integrated circuit (IC) packages. More specifically to an integrated circuit package configuration for high speed applications where the inductance of the leads is reduced or minimized in high capacity semiconductor device packages. The integrated circuit package assembly comprises a substrate, semiconductor device, insulating covering or coating, if desire, a semiconductor device retainer, lead frame, and wire bond interconnections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.