Process for making self-aligned conductive via structures

US6133635A · kind A · utility

Assignee

• Philips Electronics North America Corporation · US

Inventors

• Subhas Bothra · Fremont, US
• Jacob D. Haskell · Palo Alto, US

Key dates

• Filing date: Jun 30, 1997
• Grant date: Oct 17, 2000
• Expiry date: Jun 30, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed is a process for making a self-aligning conductive via structure in a semiconductor device. The process includes forming a first interconnect metallization layer over an oxide layer. Forming an etch stop layer over the first interconnect metallization layer. Forming a conductive via metallization layer over the etch stop layer. Forming a hard mask layer over the conductive via metallization layer. The process further includes producing a conductive via and an interconnect line, where the conductive via is formed from a portion of the conductive via metallization layer, and the interconnect line is formed from a portion of the first interconnect metallization layer. The conductive via is substantially aligned with the underlying interconnect line.