Method for fabricating capacitor-over-bit-line dynamic random access memory (DRAM) using self-aligned contact etching technology
US6136643A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 1999 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Feb 11, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A method for making capacitor-over-bit line (COB) DRAM using a self-aligned contact etching technology is achieved. After forming FET gate electrodes, sidewall spacers are formed from a first Si.sub.3 N.sub.4 etch-stop layer, while a portion of the Si.sub.3 N.sub.4 is retained as an etch-stop layer on the source/drain areas. Self-aligned contact openings are etched in a first oxide layer to the source/drain areas, and polysilicon landing plugs are formed in all the self-aligned openings. A second oxide layer is deposited and contact holes are etched to the landing plugs for bit lines. A polycide layer having a cap layer is deposited and patterned to form bit lines. A third Si.sub.3 N.sub.4 etch-stop layer is conformally deposited over the bit lines and patterned to form openings over the landing plugs for the capacitor node contacts while forming Si.sub.3 N.sub.4 sidewall spacers on the bit lines exposed in the openings. A third oxide layer is deposited, and openings having relaxed alignment tolerances, can be etched to the capacitor node contacts because the underlying third etch-stop layer prevents overetching. A conducting layer is deposited and etched back to form bottom electr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.