Method for fabricating a semiconductor device having different gate oxide layers
US6136657A · kind A · utility
10Cited by
1References
11Claims
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Key dates
| Filing date | May 20, 1999 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | May 20, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device with different gate oxide layers is provided. In this method, oxidation is controlled in accordance with the active area dimension so that the oxide grows more thinly at a wider active width in a peripheral region, and grows more thickly at a narrower active width in a cell array region. In this method, a gate pattern is formed over a semiconductor substrate having different active areas. Gate spacer are formed and an active-dimension-dependant oxidation process is then performed to grow oxide layers of different thicknesses in the cell array region and the peripheral region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.