Fabrication of interconnects with two different thicknesses
US6136686A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 1997 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Jul 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/48
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provision of differential etching of layers by, for example, an etch stop layer or implantation, allows a second trough etch to be performed in accordance with a block-out mask (which does not require high accuracy of registration) to provide troughs or recesses of different depths in layers of insulator. When the recesses or troughs are filled by metal deposition and patterned by planarization in accordance with damascene processing, structurally robust conductors of differing thicknesses may be achieved and optimized to enhance noise immunity and/or signal propagation speed in different functional regions of an integrated circuit such as the so-called array and support portions of a dynamic random access memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.