Method for planarized interconnect vias using electroless plating and CMP
US6136693A · kind A · utility
263Cited by
7References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1997 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Oct 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved and new method for fabricating conducting vias between successive layers of conductive interconnection patterns in a semiconductor integrated circuit has been developed. The method utilizes a first CMP step to form a barrier lined contact hole, deposition of copper by electroless plating into the barrier lined contact hole, and a second CMP step to remove overgrowth of copper, thus producing coplanarity between the copper surface and the surrounding insulator surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.