On-chip ESD protection in dual voltage CMOS

US6137144A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Alwin Tsao · Garland, US
• Vikas Gupta · San Leandro, US
• Gregory Charles Baldwin · Plano, US
• E. Ajith Amerasekera · Plano, US
• David B. Spratt · Plano, US
• Timothy A. Rost · Plano, US

Key dates

• Filing date: Mar 30, 1999
• Grant date: Oct 24, 2000
• Expiry date: Mar 30, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.