Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor
US6137728A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1998 |
| Grant date | Oct 24, 2000 |
| Priority date | — |
| Expiry date | Dec 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor. The source/drains of the sense field effect transistor are formed from buried doped layers (e.g. N+ in a P-doped substrate) which are formed prior to formation of the polysilicon floating gate and control gate. Lateral diffusion of dopant from the buried source/drains into the channel beneath the floating gate facilitates electron tunneling during erase and program operations, and the graded junctions of the buried source/drains lower band-to-band tunneling leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.