Method of manufacturing schottky gate transistor utilizing alignment techniques with multiple photoresist layers
US6139995A · kind A · utility
13Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2000 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Mar 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28587
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The specification describes a photolithography process using multiple exposures to form z-dimension patterns. Multiple exposures at different thickness levels are made using photomasks aligned with a latent image of alignment marks formed during the first exposure. The latent image is visible to the alignment system of commercial steppers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.