Process for forming metal oxide semiconductors including an in situ furnace gate stack with varying silicon nitride deposition rate
US6140187A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1998 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Dec 2, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/954
Abstract
The present invention provides a process for forming a dopant barrier layer in a gate stack in a semiconductor device. In one advantageous embodiment, the process includes forming a gate oxide on a semiconductor substrate, forming a gate layer on the gate oxide, and forming an ultra thin (less than about 2.5 nm) silicon nitride dopant barrier layer between the gate oxide and the gate layer. The dopant barrier layer provides an excellent barrier to inhibit dopant diffusion through the gate oxide and into the p-channel during the formation of the source/drain areas. Moreover, the formation of this dopant barrier layer and the formation of the gate layer can easily be achieved in a single furnace, if so desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.