DRAM and SRAM memory cells with repressed memory
US6141248A · kind A · utility
299Cited by
21References
83Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1999 |
| Grant date | Oct 31, 2000 |
| Priority date | — |
| Expiry date | Jul 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The transfer device of a typical DRAM cell is replaced with a transistor having an additional gate. The unique cell can be accessed as a typical DRAM cell by reading from or writing to a storage capacitor or as a nonvolatile memory by storing charges on the additional gate. Thus, a DRAM cell having a nonvolatile memory component within its cell is formed in a simple and cost effective manner. Transistors in a typical SRAM cell are also replaced by the transistors with the additional gate to form a SRAM cell having a nonvolatile component built within its cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.