Selective exclusion of silicide formation to make polysilicon resistors
US6143613A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1997 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique for processing an integrated circuit is disclosed. This technique includes the formation of a polysilicon resistor without silicide next to a polysilicon transistor gate with silicide. Prior to silicidation, an oxide layer coats both polysilicon structures. A portion of the oxide layer is removed by chemical-mechanical polishing to define a generally planar surface from the remaining oxide layer and reexposed portions of each polysilicon structure. A metal layer is deposited on the surface. The portion of the metal layer over the polysilicon resistor structure is removed through a lithographic procedure. A self-aligned silicidation procedure is performed to form a silicide from the metal remaining over the polysilicon gate structure. The formation of both structures is then completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.