Ultrathin silicon nitride containing sidewall spacers for improved transistor performance

US6144071A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Mark I. Gardner · Mabank, US
• H. Jim Fulford · Austin, US
• Charles E. May · Gresham, US

Key dates

• Filing date: Sep 3, 1998
• Grant date: Nov 7, 2000
• Expiry date: Sep 3, 2018

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/90

Abstract

A transistor is provided having a pair of sidewall spacers, each preferably including an ultrathin silicon nitride layer, adjacent to opposed sidewall surfaces of a gate conductor on a semiconductor substrate. Each spacer preferably includes a layer of thermally grown silicon nitride, and may also include a silicon dioxide layer. In an embodiment, the spacer includes a first silicon nitride layer adjacent to the sidewall surface, a silicon dioxide layer adjacent to the first silicon nitride layer, and a second silicon nitride layer adjacent to the silicon dioxide layer. Impurity distributions within the substrate may be aligned with any of the layers within the spacer, such that a distribution may be aligned with a sidewall surface or displaced outward from a sidewall surface. Such a distribution may be displaced outward by the lateral width of the spacer or by less than the lateral width of the spacer (i.e. the width of one or more layers within the spacer).