Method and apparatus for scan testing digital circuits
US6145105A · kind A · utility
22Cited by
8References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 1998 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Nov 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and digital system for testing scannable memory and combinational networks. The scannable memory is configurable into several scan chains. Each chain may have a different effective clock rate, as determined by respective clock enable signals. The method and digital system allow scan testing of digital circuits that use a single operational clock rate and several functional clock enable signals to effect slower lock operating rates. The digital system includes memory elements having scan enable and clock enable inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.