Integrated circuits with copper metallization for interconnections
US6146517A · kind A · utility
42Cited by
8References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 19, 1999 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | May 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved fill of high aspect ratio trenches by copper is obtained by first sputtering a thin nucleating film of copper deposited by physical vapor deposition, then depositing a thin seed layer of copper by chemical vapor deposition, and then completing the fill by electroplating. Stress migration of the fill is improved if the copper deposition is preceded by the deposition by CVD of a layer of titanium nitride either alone or preceded and/or followed by the deposition of tantalum by an ionized PVD source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.