Mark Hoinkis
29Patents
12h-index
60Co-inventors
80Inventor score
Filing activity: Apr 29, 1996 → Jun 19, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9114438B2 | Copper residue chamber clean | Electricity | 183 | Active |
| US9493879B2 | Selective sputtering for pattern transfer | Electricity | 132 | Active |
| US6221757A | Method of making a microelectronic structure | Electricity | 85 | Expired |
| US6218298A | Tungsten-filled deep trenches | Electricity | 53 | Expired |
| US6146517A | Integrated circuits with copper metallization for interconnections | Electricity | 42 | Expired |
| US5872694A | Method and apparatus for determining wafer warpage for optimized electrostatic chuck clamping voltage | Electricity | 32 | Expired |
| US7060619B2 | Reduction of the shear stress in copper via's in organic interlayer dielectric material | Electricity | 27 | Expired |
| US6242789A | Vertical fuse and method of fabrication | Electricity | 24 | Expired |
| US6218279A | Vertical fuse and method of fabrication | Electricity | 20 | Expired |
| US7122462B2 | Back end interconnect with a shaped interface | Electricity | 14 | Expired |
| US8871107B2 | Subtractive plasma etching of a blanket layer of metal or metal alloy | Electricity | 13 | Active |
| US7052621B2 | Bilayered metal hardmasks for use in Dual Damascene etch schemes | Emerging Cross-Sectional Technologies | 12 | Expired |
| US7241696B2 | Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer | Electricity | 12 | Expired |
| US6057236A | CVD/PVD method of filling structures using discontinuous CVD AL liner | Electricity | 11 | Expired |
| US6539625B2 | Chromium adhesion layer for copper vias in low-k technology | Emerging Cross-Sectional Technologies | 10 | Expired |
| US6383929B1 | Copper vias in low-k technology | Electricity | 10 | Expired |
| US7241681B2 | Bilayered metal hardmasks for use in dual damascene etch schemes | Emerging Cross-Sectional Technologies | 9 | Expired |
| US6870263B1 | Device interconnection | Electricity | 8 | Expired |
| US7091612B2 | Dual damascene structure and method | Electricity | 5 | Expired |
| US9171796B1 | Sidewall image transfer for heavy metal patterning in integrated circuits | Electricity | 5 | Active |
| US9484220B2 | Sputter etch processing for heavy metal patterning in integrated circuits | Electricity | 4 | Active |
| US5989633A | Process for overcoming CVD aluminum selectivity loss with warm PVD aluminum | Electricity | 3 | Expired |
| US6960835B2 | Stress-relief layer for semiconductor applications | Electricity | 3 | Expired |
| US6864171B1 | Via density rules | Electricity | 3 | Expired |
| US7368804B2 | Method and apparatus of stress relief in semiconductor structures | Electricity | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.