Parallel read and verify for floating gate memory device
US6147910A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1999 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Aug 31, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page mode flash memory or floating gate memory device, including a page buffer based upon low current bit latches, and additional capabilities for parallel read and parallel program verify operations. The present device includes bit latch circuitry and/or method steps that facilitate such parallel operations and avoid data conflicts. Circuitry for separate read signals can serve to isolate the operations. Additionally, circuitry tied to the data verification signal can also be used. A diode type device can be used to isolate signal conditions that might indicate the cell does not need to be programmed. Bit-by-bit precharging of the bit lines can also be employed in order to save precharging power. Additionally, the large capacitance of the dataline might be used to delay discharging a particular dataline, and thereby allow a latch enabling signal to go high, thus eliminating the need for further isolation circuitry, or the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.