System and method for automatic generation of gate-level descriptions from table-based descriptions for electronic design automation
US6148436A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Automatic generation of gate-level descriptions from table-based descriptions within the field of electronic design automation. The gate-level and structural descriptions are used for test generation processes and some formal verification processes. For combinational table-based descriptions, ordered ternary decision diagram (OTDD) graphs are used with novel input reordering to extract prime, non-redundant cube sets that can include high level functions (e.g., XOR, XNOR, MUX). For sequential table-based descriptions, a reduced or "clock" based OTDD graph is generated from which data and clock signals are identified and characterized. Input reordering is done and a complete sequential OTDD graph is generated, followed by port separation and characterization of the sequential element. Clock and data functions are then constructed on a port-by-port basis using the prime, non-redundant cube set generation processes of the combinational logic phase. By providing an automatic generation process for the gate-level and structural descriptions, processes for verifying equivalence between the gate-level and structural descriptions and the table-based descriptions can be eliminated from the d…
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