Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions

US6150222A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Mark I. Gardner · Mabank, US
• Thien T. Nguyen · Fremont, US
• Charles E. May · Gresham, US

Key dates

• Filing date: Jan 7, 1999
• Grant date: Nov 21, 2000
• Expiry date: Jan 7, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6725

Abstract

The present invention is directed to a transistor formed above a layer of a dielectric material and a method of making same. In one illustrative embodiment, the method comprises forming a first layer of dielectric material, forming a plurality of source/drain regions comprised of polysilicon above said first layer of dielectric material and between said source/drain regions, and forming a second layer of dielectric material above said first layer of dielectric material. The method further comprises forming a layer of polysilicon above the second layer of dielectric material, forming a gate dielectric above said layer of polysilicon, and forming a gate conductor above said gate dielectric. The transistor structure is comprised of a first layer of dielectric material, a plurality of source/drain regions positioned above the first layer of dielectric material, a second layer of dielectric material positioned above the first layer of dielectric material, and a layer of polysilicon positioned above the second layer of dielectric material and between said source/drain regions. The structure further comprises a gate dielectric positioned above the layer of polysilicon and a gate conductor…