User-controlled delay circuit for a programmable logic device
US6150863A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1998 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Apr 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input block is provided that includes a user-controlled, variable-delay input circuit. The input circuit is adapted to receive an input signal and to output a delayed version of the input signal on an output node. A number of control signals dictate the amount of delay imposed on the input signal. The control signals, and therefore the amount of delay, are established using a control-signal generator. The generator can be used to actively alter the delay. In one embodiment, the control signal generator is implemented as a feedback circuit that automatically matches the delay period of the delay circuit with the delay period of a distributed clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.