Cell capacitors, memory cells, memory arrays, and method of fabrication
US6153903A · kind A · utility
11Cited by
24References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 3, 1998 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Dec 3, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A masking and etching technique during the formation of a memory cell capacitor which utilizes an etching technique to utilize a maximum surface area over the memory cell and to form thin spacers to pattern separation walls between capacitors. This technique results in efficient space utilization which, in turn, results in an increase in the surface area of the capacitor for an increased memory cell capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.