Electrostatic discharge protection circuit
US6153913A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1999 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides an ESD protection circuit, which is formed on a semiconductor substrate. There is at least one MOS transistor branches out at a place between an I/O port and an internal circuit. The MOS transistor includes a drain region, a source region, a gate oxide layer, and a gate electrode. The source and the drain regions are formed in the substrate and located on each side of the gate electrode. An insulating layer is formed over the substrate to cover the MOS transistor. A drain contact is formed in the insulating layer with a contact to the drain region of the MOS transistor so that the drain region can be coupled to the internal circuit through the drain contact. A source contact is formed in the insulating layer with a contact to the source region of the MOS transistor so that the source region can be coupled to the I/O port through the source contact. Several floating silicide blocks is located between the insulating layer and the substrate at the drain region. The silicide blocks are about evenly distributed within the drain region, and preferably distributed in a structure like grid nodes with a shift for the adjacent node row. The silicide includes self-align…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.