Disposition tool for factory process control
US6154711A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1997 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Dec 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing semiconductor wafers using a simulation tool to determine a set of predicted wafer electrical test parameters. The set of predicted wafer electrical test parameters are compared with wafer electrical test specifications tabulated for each process during the manufacturing process. During the comparison, it is determined whether the predicted wafer electrical test parameters are within the specifications for the process and circuit simulations are then conducted using the predicted wafer electrical test parameters. Device performance is predicted from the circuit simulations and the disposition of the wafer lot is determined utilizing tabulated from a disposition performance table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.