Trilayer lift-off process for semiconductor device metallization
US6156665A · kind A · utility
15Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1998 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Apr 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/30621
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The specification describes a trilevel resist technique for defining metallization patterns by lift-off. The trilevel resist comprises two standard photoresist levels separated by a thin silicon oxide layer with approximate composition SiO.sub.2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.