High-reliability damascene interconnect formation for semiconductor fabrication
US6157081A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1999 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Mar 10, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high-reliability damascene interconnect structure and a method for forming the same are provided. An interlevel dielectric is formed over a semiconductor topography, and trenches for interconnects and/or vias are formed in the interlevel dielectric. A trench liner may then be deposited, followed by deposition of a low-resistance metal such as copper. The low-resistance metal deposition is preferably stopped before the trenches are entirely filled. Portions of the metal and trench liner external to the trenches are subsequently removed, such that low-resistance metal interconnect portions are formed. A high-melting-point metal, such as tungsten, is deposited over upper surfaces of the interconnect portions and interlevel dielectric. Portions of the high-melting-point metal are removed to form interconnects having a low-resistance metal lower portion and a high-melting-point metal upper portion. In one embodiment, the extrusion-prone lowresistance metal is removed from the vicinity of a ready extrusion path between the interlevel dielectric and an overlying dielectric. In another embodiment, the overlying metal is believed to prevent extrusion of the low-resistance metal by bonding…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.