Redundancy circuit and method for semiconductor memory
US6157584A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 20, 1999 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | May 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy configurations is described in which a redundant element is able to overpower a defective element without the need for physical disconnection or logical deselection and in which plural redundant rows (or columns) are provided to replace more than one defective row (or column) in an array or subarray. Redundancy configurations are further described in which a redundant element is able to overpower a defective element without the need for physical disconnection or logical deselection and in which a given redundant row (or column) may replace a defective row (or column) in one of plural subarrays representing distinct sets of rows (or columns).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.