Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space
US6157996A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1997 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Nov 13, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30185
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor for executing computer instructions including, in one embodiment, a machine specific register (MSR) which includes a predicated execution field and an instruction decoder. The decoder is coupled to the MSR and configured to detect predicated execution information contained in the computer instruction and to include conditional execution information in the decoded instruction upon detecting an appropriate setting in the predicated execution field of the MSR. The processor further includes a first execution unit. The first execution unit is configured to detect and evaluate the conditional execution information in the decoded instruction and, if present, to execute the decoded instruction only if a condition represented by the conditional execution information is true. In another embodiment, the processor includes a standard register set and an extended register set, which includes the standard register set. The decoder is configured to search the computer instruction for an extended register indicator upon detecting an appropriate setting in the extended register field of the MSR. The decoder is further configured to fetch, upon detecting the extended register indicator,…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.