Method of testing an integrated circuit having a memory and a test circuit
US6158029A · kind A · utility
4Cited by
5References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 1999 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Sep 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory can be tested by the test circuit and is connected to the latter via data lines, address lines, and control lines. At least one of the control lines is connected via a controlled switching device. The switching device can be controlled via an external terminal of the integrated circuit, with the result that the signal characteristic on the corresponding line and thus the timing of the test can be influenced externally. The invention is particularly suitable for implementing self-tests of embedded memory cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.