Way to fabricate the self-aligned T-shape gate to reduce gate resistivity
US6159781A · kind A · utility
29Cited by
18References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1998 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Oct 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of fabricating a semiconductor field effect transistor, wherein the gate has a short foot portion in contact with the semiconductor substrate for a short gate length and consequent low capacitance, and a large amount of metal in a contact portion for low gate resistance. Salicides are formed on the T-gate source on drain contact areas resulting in large, low resistance contact areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.