Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant

US6159782A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Qi Xiang · San Jose, US
• Ming-Ren Lin · Cupertino, US

Key dates

• Filing date: Aug 5, 1999
• Grant date: Dec 12, 2000
• Expiry date: Aug 5, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process, such as an activation anneal or a salicidation anneal of the source and drain of the field effect transistor, using relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and amorphous gate electrode material, such as amorphous silicon, is deposited to fill the gate opening after the layer of dielectric has been deposited. Dual gates for both an N-channel field effect transistor and a P-channel field effect transistor are formed by doping the amorphous gate electrode material with an N-type dopant for an N-channel field effect transistor, and by doping the amorphous ga…