Low voltage junction and high voltage junction optimization for flash memory

US6159795A · kind A · utility

Assignees

• Advanced Micro Devices, Inc. · US
• FUJITSU LIMITED · JP

Inventors

• Masaaki Higashitani · Cupertino, US
• Hao Fang · Cupertino, US
• Narbeh Derhacobian · Belmont, US

Key dates

• Filing date: Jul 2, 1998
• Grant date: Dec 12, 2000
• Expiry date: Jul 2, 2018

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/976

Abstract

An intermediate implant step is performed to optimize the performance of the transistors in the peripheral portion of a floating gate type memory integrated circuit. The polysilicon layer (Poly 1) that forms the floating gate in the respective floating gate type memory devices prevents penetration of the optimizing implant into the core region in which the floating gate memory devices are formed. This permits the optimization implant to be performed without the need for an additional mask, thus reducing costs and production time.